1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming replacement gate structures for NFET semiconductor devices and devices having such replacement gate structures.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET is a device that typically includes a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. If a voltage that is less than the threshold voltage of the device is applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage that is equal to or greater than the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a planar FET, which has a planar structure, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. More specifically, in a FinFET, a generally vertically positioned, fin-shaped active area is formed and a gate electrode encloses both of the sides and the upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a three-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the depletion width under the channel and thereby reduce so-called short channel effects. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
For many previous device technology generations, the gate electrode structures of most transistor elements has been comprised of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-20 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in an HK/MG gate electrode structure. For example, in some transistor element designs, a high-k gate insulation layer may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like. Furthermore, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—may be used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like.
One well-known processing method that has been used for forming either planar or 3D transistors with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. FIGS. 1A-1D depict one illustrative prior art method for forming an HK/MG replacement gate structure using a gate last technique for an illustrative planar transistor device 100. As shown in FIG. 1A, the process includes the formation of a basic transistor structure 100 above a semiconducting substrate 10 in an active area defined by a shallow trench isolation structure 11. At the point of fabrication depicted in FIG. 1A, the device 100 includes a sacrificial gate insulation layer 12, a dummy or sacrificial gate electrode 14, sidewall spacers 16, a layer of insulating material 17 and source/drain regions 18 formed in the substrate 10. The various components and structures of the device 100 may be formed using a variety of different materials and by performing a variety of known techniques. For example, the sacrificial gate insulation layer 12 may be comprised of silicon dioxide, the sacrificial gate electrode 14 may be comprised of polysilicon, the sidewall spacers 16 may be comprised of silicon nitride and the layer of insulating material 17 may be comprised of silicon dioxide. The source/drain regions 18 may be comprised of implanted dopant materials (N-type dopants for NFET devices and P-type dopants for PFET devices) that are implanted into the substrate 10 using known masking and ion implantation techniques. Of course, those skilled in the art will recognize that there are other features of the transistor 100 that are not depicted in the drawings for purposes of clarity. For example, so-called halo implant regions are not depicted in the drawings, as well as various layers or regions of silicon/germanium that are typically found in high performance PFET transistors. At the point of fabrication depicted in FIG. 1A, the various structures of the device 100 have been formed and a chemical mechanical polishing process (CMP) has been performed to remove any materials above the sacrificial gate electrode 14 (such as a protective cap layer (not shown) comprised of silicon nitride) so that at least the sacrificial gate electrode 14 may be removed.
As shown in FIG. 1B, one or more etching processes are performed to remove the sacrificial gate electrode 14 and the sacrificial gate insulation layer 12 to thereby define a gate cavity 20 where a replacement gate structure will subsequently be formed. A masking layer that may be employed in such etching processes is not depicted for purposes of clarity. Typically, the sacrificial gate insulation layer 12 is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 12 may not be removed in all applications.
Next, as shown in FIG. 1C, various layers of material that will constitute a replacement gate structure 30 are formed in the gate cavity 20. The materials used for such replacement gate structures 30 may vary depending upon the particular application. Even in cases where the sacrificial gate insulation layer 12 is intentionally removed, there will typically be a very thin native oxide layer (not shown) that forms on the substrate 10 within the gate cavity 20. In one illustrative example, the replacement gate structure 30 is comprised of a high-k gate insulation layer 30A, such as hafnium oxide, and first, second and third metal layers 30B, 30C and 30D, respectively, that are conformably deposited above the device and in the gate cavity 20. Also depicted in FIG. 1C is an illustrative bulk metal layer 30E, such as aluminum, that is deposited so as to fill the remaining unfilled portion of the gate cavity 20. Ultimately, as shown in FIG. 1D, one or more CMP processes are performed to remove excess portions of the gate insulation layer 30A and the layers 30B, 30C, 30D and 30E positioned outside of the gate cavity 20 to thereby define the replacement gate structure 30. The various layers of the replacement gate structure 30 may be made of a variety of different materials depending upon the particular application and/or the type of device under construction.
FIG. 1E is an enlarged view of an illustrative replacement gate structure 100NG for an illustrative NFET transistor 100N. In one illustrative example, the replacement gate structure 100NG is comprised of a high-k gate insulation layer 40, such as hafnium oxide, having a thickness of approximately 2 nm or less, a first metal layer 42 (e.g., a layer of titanium nitride (TiN) with a thickness of about 1-2 nm), a second metal layer 44 (e.g., a layer of tantalum nitride (TaN) with a thickness of about 1-2), a third metal layer 46 (e.g., a layer of titanium-aluminum (TiAl (1:1)) with a thickness of about 10 nm), a fourth metal layer 48 (e.g., a layer of titanium (Ti) with a thickness of about 6 nm) and a bulk metal layer 50, such as aluminum. For ease of illustration, other than the bulk metal layer 50, the portions of the various layers of material shown in FIG. 1E that are deposited above the upper surface of the layer of insulating material 17 are not depicted in FIG. 1E. An illustrative PFET device (not shown) typically includes an additional layer of metal (not shown) to those formed for the NFET device 100N, such as a relatively thick layer of titanium nitride (with a thickness of about 5 nm) positioned between the second metal layer 44 (TaN) and the third metal layer 46 (TiAl (1:1)). The gate insulation layer 40 may be formed by performing a conformal chemical vapor deposition (CVD) process. The various layers of metal shown in FIG. 1E may be formed by performing various physical vapor deposition (PVD) processes using the appropriate metal targets. In forming integrated circuit products that have both NFET and PFET devices, with the exception of the additional layer of metal noted above for the PFET device, all of the materials are formed on both of the NFET and PFET devices in common process operations. When it is time to form the additional layer of metal for the PFET devices only, the NFET devices are masked using known masking techniques.
In the NFET device 100N, the aluminum in the third metal layer 46 (titanium-aluminum (TiAl (1:1)) is the work-function adjusting material, i.e., it is used to reduce the threshold voltage of the NFET device 100N. The work-function adjusting material for the PFET device (not shown) is the first metal layer 42 (titanium nitride (TiN)). More specifically, the aluminum in the third metal layer 46 (TiAl) is used to lower the work-function of the NFET device 100N, which is desirable for such an NFET device. However, aluminum also tends to lower the work-function for the PFET device, which is undesirable for the PFET device. Thus, the PFET device includes the additional layer of metal, e.g., the relatively thick layer of titanium nitride positioned between the second metal layer 44 (TaN) and the third metal layer 46 (TiAl) so as to block or reduce the chances of aluminum migrating toward the channel region of the PFET device.
As shown in FIG. 1F, after the various layers shown in FIG. 1E are formed, a reflow or heating process is performed so as to drive aluminum, as schematically depicted by the region 60, from the third metal layer 46 (TiAl) and the bulk aluminum layer 50 toward the channel region of the NFET device 100N. The reflow process may be performed at a temperature of about 400° C. for a duration of about 2 minutes. After the reflow process, titanium-aluminum (TiAl) will readily form just above the gate insulation layer 40 due to the migration of aluminum. Unfortunately, this thermal diffusion of aluminum is a difficult process to control and stop. There are several risks involved in adjusting the work-function of the NFET device 100N using this approach. For example, if the diffusion of aluminum is not precisely controlled so as to limit the extent of the aluminum diffusion, problems such as gate leakage, gate punch through (aluminum spiking into the silicon channel region) and potential degradation of the PFET device may occur.
The present disclosure is directed to various methods of forming replacement gate structures for NFET semiconductor devices and devices having such replacement gate structures that may avoid, or at least reduce, the effects of one or more of the problems identified above.